LVS issue with MOS bulk connection in XFAB PDK schematic-driven layout
Luca
Tuesday 21st April 2026
Dear support,
I am using the XFAB XH018 PDK in schematic-driven layout mode, and I am having an LVS issue related to the NMOS bulk connection.
In the PDK layout cell for the NMOS (for example the ne device), the bulk contact is not included in the layout and therefore has to be added manually.
I first tried adding the bulk connection at the top-cell level and naming the node M1/B. Then I also added the bulk contact inside the NE cell and named the node B. In both cases, the connection is still not recognized by LVS.
The LVS report keeps showing: "missing connection on M1/B".
Could you please clarify how the bulk connection is expected to be implemented for this PDK in LayoutEditor when the bulk tie is not included in the original device layout?
Should the bulk node be named in a specific way, or does it need to be assigned manually during extraction/LVS setup when using schematic-driven layout?
Thank you.
Luca
Jürgen LayoutEditorFull Tuesday 21st April 2026
Dear Luca, please have a look at the used layers. On which layer 'B' label is placed in the 'NE' cell? Is this layer set up as a conductive layer in the layer setup. On which layer the "M1/B" label is placed? Is it marked as a conductive layer as well? Is there a path between both labels and are all used layers marked as conductive or via layer? There are the items the LVS checks. At least one of it is not correct in your case. The node mode on the LVS page highlights all shapes the LVS assumes to be electrical connected. This may help to find out why the LVS assumes that this mentioned connection is missing.
Luca
Tuesday 21st April 2026
Dear Jürgen,
Thank you for your quick reply.
As I mentioned before, unfortunately the B label is not present in the ne device layout provided by the PDK. The MOS layout cell only includes the source, gate, and drain connections, even though the corresponding schematic is a 4-terminal device, including the bulk.
Since the bulk terminal is not implemented in the original layout cell, I added the bulk connection manually in the layout and placed the corresponding label on the MET1 layer, the same conductive layer used for the S, and D connections.
LVS works correctly for all the other terminals. The issue only affects the bulk terminal, which is manually added in the layout but is present in the schematic symbol provided by the PDK.
Thank you in advance for your support.
Jürgen LayoutEditorFull Wednesday 22nd April 2026
Ah, of course that will not work. Any pin connection must be labeled within the cell. The extraction tool/LVS identifies any label on a conductive layer within a cell as its pins. Any shape on a conductive layer not labeled must not be connected to any ahpe outside the cell. So you nedd ether label the bulk within the cell, or remove the bulk connection from the schematic or just ignore bulk connection error in the LVS.