Support Forum
"Layout versus Loaded Netlist" errors that I cannot resolve
Ted
Sunday 23rd January 2022
Attachments:
(only for registered users)
Selection_047.png
I made a schematic and a corresponding layout in LayoutEditor. I want the see if I could compare the extracted netlist to the spice netlist, but I have errors that I can't get rid of. Here's what I did. Hopefully you can tell me if I'm doing anything wrong. (1) Start up LayoutEditor and run Technology/SkyWater/sky130A/layerMacro.layout from the utilities menu (2) Open buf.GDS or buf.GDS.lec, and select the "buf" cell (3) From the netlist pane, change "displayed netlist" to "loaded" (4) From the "import" section I've tried adding sky130_fd_sc_hd.lel, and I've tried without (5) Hit "load netlist" and select buf.sp (6) Click the "Edit Netlist" button to look at what was loaded (6a) If I look at the "LayoutEditor Dump" section, it looks like the connectivity was read in correctly: ``` DEVICES L1 (sky130_fd_sc_hd__inv_1, placed) connections{->0 ->2 ->3 ->4 ->5 ->7 } parameter[ ] L2 (sky130_fd_sc_hd__inv_1, placed) connections{->7 ->2 ->3 ->4 ->5 ->1 } parameter[ ] ``` (6b) The "spice" section shows completely different connectivity: ``` XL1 0 0 0 0 0 0 sky130_fd_sc_hd__inv_1 XL2 Node_2 Node_2 Node_2 Node_2 Node_2 Node_2 sky130_fd_sc_hd__inv_1 ``` (6c) ngspice netlist shows duplicates ``` *start of netlist XL1 0 0 0 0 0 0 sky130_fd_sc_hd__inv_1 XL2 Node_2 Node_2 Node_2 Node_2 Node_2 Node_2 sky130_fd_sc_hd__inv_1 *NGspice specific part XL1 0 0 0 0 0 0 sky130_fd_sc_hd__inv_1 XL2 Node_2 Node_2 Node_2 Node_2 Node_2 Node_2 sky130_fd_sc_hd__inv_1 *end of netlist ``` (7) In the "Extraction" tab I click the "Build Connections" button and wait for it to finish (7a) The extracted netlist looks correct: ``` *start of netlist XL2 Node_1 VGND VNB VPB VPWR out sky130_fd_sc_hd__inv_1 XL1 in VGND VNB VPB VPWR Node_1 sky130_fd_sc_hd__inv_1 *end of netlist ``` (8) Click on the "Layout versus Loaded Netlist" button and I get errors I don't know how to resolve. See the attached picture.  (9) I was curious if I could ignore these errors, so I tried breaking the connection between the two inverters. Although the extracted netlist showed the broken connection, no additional error about connectivity showed up in the list of errors. I don't know how to attach most of the involved files, as most of the extensions are not supported, so I'll send them as an email
Sunday 23rd January 2022
Attachments:
(only for registered users)
Selection_047.png
I made a schematic and a corresponding layout in LayoutEditor. I want the see if I could compare the extracted netlist to the spice netlist, but I have errors that I can't get rid of. Here's what I did. Hopefully you can tell me if I'm doing anything wrong. (1) Start up LayoutEditor and run Technology/SkyWater/sky130A/layerMacro.layout from the utilities menu (2) Open buf.GDS or buf.GDS.lec, and select the "buf" cell (3) From the netlist pane, change "displayed netlist" to "loaded" (4) From the "import" section I've tried adding sky130_fd_sc_hd.lel, and I've tried without (5) Hit "load netlist" and select buf.sp (6) Click the "Edit Netlist" button to look at what was loaded (6a) If I look at the "LayoutEditor Dump" section, it looks like the connectivity was read in correctly: ``` DEVICES L1 (sky130_fd_sc_hd__inv_1, placed) connections{->0 ->2 ->3 ->4 ->5 ->7 } parameter[ ] L2 (sky130_fd_sc_hd__inv_1, placed) connections{->7 ->2 ->3 ->4 ->5 ->1 } parameter[ ] ``` (6b) The "spice" section shows completely different connectivity: ``` XL1 0 0 0 0 0 0 sky130_fd_sc_hd__inv_1 XL2 Node_2 Node_2 Node_2 Node_2 Node_2 Node_2 sky130_fd_sc_hd__inv_1 ``` (6c) ngspice netlist shows duplicates ``` *start of netlist XL1 0 0 0 0 0 0 sky130_fd_sc_hd__inv_1 XL2 Node_2 Node_2 Node_2 Node_2 Node_2 Node_2 sky130_fd_sc_hd__inv_1 *NGspice specific part XL1 0 0 0 0 0 0 sky130_fd_sc_hd__inv_1 XL2 Node_2 Node_2 Node_2 Node_2 Node_2 Node_2 sky130_fd_sc_hd__inv_1 *end of netlist ``` (7) In the "Extraction" tab I click the "Build Connections" button and wait for it to finish (7a) The extracted netlist looks correct: ``` *start of netlist XL2 Node_1 VGND VNB VPB VPWR out sky130_fd_sc_hd__inv_1 XL1 in VGND VNB VPB VPWR Node_1 sky130_fd_sc_hd__inv_1 *end of netlist ``` (8) Click on the "Layout versus Loaded Netlist" button and I get errors I don't know how to resolve. See the attached picture.  (9) I was curious if I could ignore these errors, so I tried breaking the connection between the two inverters. Although the extracted netlist showed the broken connection, no additional error about connectivity showed up in the list of errors. I don't know how to attach most of the involved files, as most of the extensions are not supported, so I'll send them as an email
Jürgen
LayoutEditorFull
Sunday 23rd January 2022
Attachments:
(only for registered users)
setup.png
lvn.png
First of all, if you use the SchematicEditor to create the netlist, you don't need to use spice the transfer the netlist from the schematic window to the layout window. Both windows are linked and the netlist is transfered in an automatic way. The Spice-format is here just an unnecessary file to transfer the data and will need additional things to setup to work properly. A Spice netlist will not contain all relevant information to perform a netlist driven layout or even a LVS. The missing information needs to be provided by a library. In the LayoutEditor window you can set additional libraries just for such netlist import. But this step is mostly not require in case the SchematicEditor is setup properly. In the setup you can define that the SchematicEditor libraries should be used for this import as well: (setup/netlist/import/use component libraries)  In your example the spice netlist is incomplete. It does not contain the information on the used subcircuits. For your example the netlist should look like this: ```SPICE *ngspice /home/tedh/layout_editor/branch_mpw5/sky130/designs/native/buf.les generated by the LayoutEditor (www.LayoutEditor.com) .subckt buf in out XL1 in VGND VNB VPB VPWR Node_2 sky130_fd_sc_hd__inv_1 XL2 Node_2 VGND VNB VPB VPWR out sky130_fd_sc_hd__inv_1 .ends .subckt sky130_fd_sc_hd__inv_1 A VGND VNB VPB VPWR Y X0 VGND A Y VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u X1 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u .ends ``` The lines stating with *X0* and *X1* are optional in case you just want to check the cell *buf*. But the line *.subckt* line is required as it contains the labeling of the pin names of the subcircuit. A *.include* statement to the spice library file would be useful here, but sadly its support is missing in the current stable release. Its support will be added and will be available in any release from now. A correct import should look like: ``` DEVICES L1 (sky130_fd_sc_hd__inv_1, placed) connections{A->0 VGND->3 VNB->4 VPB->5 VPWR->6 Y->7 } L2 (sky130_fd_sc_hd__inv_1, placed) connections{A->7 VGND->3 VNB->4 VPB->5 VPWR->6 Y->1 } ``` When going through your example I also found a small issue reading the output configuration. This will be fixed with the todays development release as well. It will only effect the shipped Skywater PDK having the output as parameter without an *x* character. Most other PDK use a own device for any available output. With the correctly loaded spice netlist the LVS result should look like this:  Just the error on the additional power connections are left. You can ignore these errors, as these connection are not labeled in the layout cells of the technology and could not be checked. The mentioned improvements are available in the todays development release. Download later today under this link: [https://layouteditor.com/download?release=latest](https://layouteditor.com/download?release=latest)
LayoutEditorFull
Sunday 23rd January 2022
Attachments:
(only for registered users)
setup.png
lvn.png
First of all, if you use the SchematicEditor to create the netlist, you don't need to use spice the transfer the netlist from the schematic window to the layout window. Both windows are linked and the netlist is transfered in an automatic way. The Spice-format is here just an unnecessary file to transfer the data and will need additional things to setup to work properly. A Spice netlist will not contain all relevant information to perform a netlist driven layout or even a LVS. The missing information needs to be provided by a library. In the LayoutEditor window you can set additional libraries just for such netlist import. But this step is mostly not require in case the SchematicEditor is setup properly. In the setup you can define that the SchematicEditor libraries should be used for this import as well: (setup/netlist/import/use component libraries)  In your example the spice netlist is incomplete. It does not contain the information on the used subcircuits. For your example the netlist should look like this: ```SPICE *ngspice /home/tedh/layout_editor/branch_mpw5/sky130/designs/native/buf.les generated by the LayoutEditor (www.LayoutEditor.com) .subckt buf in out XL1 in VGND VNB VPB VPWR Node_2 sky130_fd_sc_hd__inv_1 XL2 Node_2 VGND VNB VPB VPWR out sky130_fd_sc_hd__inv_1 .ends .subckt sky130_fd_sc_hd__inv_1 A VGND VNB VPB VPWR Y X0 VGND A Y VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u X1 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u .ends ``` The lines stating with *X0* and *X1* are optional in case you just want to check the cell *buf*. But the line *.subckt* line is required as it contains the labeling of the pin names of the subcircuit. A *.include* statement to the spice library file would be useful here, but sadly its support is missing in the current stable release. Its support will be added and will be available in any release from now. A correct import should look like: ``` DEVICES L1 (sky130_fd_sc_hd__inv_1, placed) connections{A->0 VGND->3 VNB->4 VPB->5 VPWR->6 Y->7 } L2 (sky130_fd_sc_hd__inv_1, placed) connections{A->7 VGND->3 VNB->4 VPB->5 VPWR->6 Y->1 } ``` When going through your example I also found a small issue reading the output configuration. This will be fixed with the todays development release as well. It will only effect the shipped Skywater PDK having the output as parameter without an *x* character. Most other PDK use a own device for any available output. With the correctly loaded spice netlist the LVS result should look like this:  Just the error on the additional power connections are left. You can ignore these errors, as these connection are not labeled in the layout cells of the technology and could not be checked. The mentioned improvements are available in the todays development release. Download later today under this link: [https://layouteditor.com/download?release=latest](https://layouteditor.com/download?release=latest)
Ted
Sunday 23rd January 2022 Cool. Your suggestions resolved everything. I've compared to the schematic instead of a netlist before and it works great. I was trying out the netlist for designs created outside of LayoutEditor where I don't have a schematic. (In the case of a layout created outside of LayoutEditor I mimicked your sref attributes in the gds, and it seems to work). I wouldn't expect LayoutEditor to recognize foreign devices, but I was hoping I could get it to work with cell references, and I can. I don't expect to use any parameterized layout views or model names, like `sky130_fd_sc_hd__inv_$output`. Thanks
Sunday 23rd January 2022 Cool. Your suggestions resolved everything. I've compared to the schematic instead of a netlist before and it works great. I was trying out the netlist for designs created outside of LayoutEditor where I don't have a schematic. (In the case of a layout created outside of LayoutEditor I mimicked your sref attributes in the gds, and it seems to work). I wouldn't expect LayoutEditor to recognize foreign devices, but I was hoping I could get it to work with cell references, and I can. I don't expect to use any parameterized layout views or model names, like `sky130_fd_sc_hd__inv_$output`. Thanks