Thursday 2nd December 2021
For reference, I was trying to make layout for a std cell, and using the built-in extraction functionality. I have VDD port for the pmos supply and VNW port for the pmos bulk, since those are what the netlist has. The bulk connection does not actually exist in the layout, and would have to be added with an abutted cell.
The problems I ran into are:
1) I appears I can only have one label for each node. When I tried labeling a node with both ‘VDD’ and ‘VNW’, only one label was recognized. In my case it may not be necessary, but I can imagine wanting it in the future. (usually there’s some sort of accompanying “lvs short” property in the schematic).
2)If I move the ‘VNW’ label to the nwell layer, drawn over an nwell rectangle, it’s still not recognized – I still get the message “external node VNW not labeled”. Are labels only recognized on routing layers?
3) I’m trying the evaluation version and text that says “Generated with the LayoutEditor (This message will NOT added in any commercial version of the LayoutEditor.)” keeps getting added everywhere, which is understandable. The problems is (related to problem (1)) that they keep getting added to the layers I’m drawing on, so in the extraction pane I get the dual errors:
* “additional connection pch/Generated with the LayoutEditor (This message will NOT added in any commercial version of the LayoutEditor.)”
* “external node VDD not labeled”
Right know I can work around it by moving those additional messages to another layer, like the “error” layer, but so many of those texts pop up that’s it very cumbersome.
Jürgen LayoutEditorFull Friday 3rd December 2021
Any net can have exactly one name. If there is more than one name on a net, just one of these names is used in the extracted netlist. If your design requires a short like a metal resistor, put a metal segment on a different datatype between both ports and list this datatype inside the setup/netlist/layoutextraction/ignor_datatype_for_building_connections. Then the extraction tool will not put both ports on a single net.
For extraction only layers are respected that are on a layer marked as via or conductor in the layer setup. All other text is handled as info text and is ignored during extraction. So it can be required to setup the nwell layer as a conductive layer to get the correct extracted netlist.
In case you are using the free version of the LayoutEditor without a license key, the text element "Generated with the LayoutEditor (This message will NOT added in any commercial version of the LayoutEditor.)” will be added during save to any cell. when srtored to GDS. When loading this GDS file this text element will be ignored and not loaded. So the text will only be visible in case an intermediate storage of the design was done. There is an example macro shipped with the LayoutEditor ( *removeText.layout* ) that can remove a certain text from the design. So by using it these text element can be removed by a single click, if required.
Ted
Friday 3rd December 2021
Thanks. You've given me enough information to fix all of my problems.