Can't get a vectored port to netlist out correctly
Wednesday 1st December 2021
I have a component with a vectored port. The port name is 'cntr<3:0>'. If I connect it to 'foo<6:3>' the netlist is as expected:
Xsub1 vdd vdd vss hi lo c<0> c<1> Node_5 Node_4 Node_3 Node_2 foo<3> foo<4> foo<5> foo<6> hi hi ldo_c ldo_fb Node_17 dac_bit_msb
If I connect the port to 'hi,3*lo' or 'hi,lo,lo,lo' it netlists out as:
Xsub1 vdd vdd vss hi lo c<0> c<1> Node_5 Node_4 Node_3 Node_2 bus1::lo bus1::lo bus1::lo bus1::hi hi hi ldo_c ldo_fb Node_17 dac_bit_msb
The nets bus1::lo andd bus1::hi don't match any other nets and are treated as a floating net by the simulator.
Is there any way to get that connection to netlist out as 'lo lo lo hi' ?
Jürgen LayoutEditorFull Wednesday 1st December 2021Attachments: (only for registered users) Screenshot_20211201_210704.png
You need to connect the bus signals to *lo* and *hi* net like: